State of the art low capture power methodology
Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Ranjan Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto · 2011
Power consumption during test can be significantly higher than during normal functional mode. This paper presents a low power Automated Test Pattern Generation (ATPG) flow for managing capture power in today's power critical designs. It introduces a novel method for sequentially enabling the on-chip clock controllers to generate accurate low power ATPG patterns respecting the power specifications of the design. The effectiveness of the method is demonstrated on several industrial designs that show up power issues during test mode.