VLSI Testing for High Reliability: Mixing IDDQ TestingWith Logic Testing
Seongmin Hwang, Rochit Rajsuman · VLSI design · 1997
In this paper, we examine the effectiveness of combined logic and IDDQ testing to detect stuck‐at and bridging faults. The stuck‐at faults are detected by the logic test and IDDQ testing detects bridging faults. Near minimal stuck‐at test sets are used for this combined logic and IDQQ test environment. These near minimal stuck‐at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS ′85 and ISCAS ′89 benchmark circuits under this combined test environment. A comparison is given for the fault coverage obtained under this combined test environment with other studies based on pure logic test and IDDQ test. Also, the results of IDDQ based test sets (vectors generated specifically for IDDQ testing) are compared with that of stuck‐at test sets. Finally, we present a case study on a microprogrammed processor using a functional test set to detect bridging faults in IDDQ testing.