Fast synchronization for chip multiprocessors
Jack Sampson, Rubén Arístides González Crespo, Jean-François Collard⋆, Norman Paul Jouppi, Mike Schlansker · ACM SIGARCH Computer Architecture News · 2005
This paper presents a novel mechanism for barrier synchronization on chip multi-processors (CMPs). By forcing the invalidation of selected I-cache lines, this mechanism starves threads and thus forces their execution to stop. Threads are let free when all have entered the barrier.We evaluated this mechanism using SMTSim and report much better (and most importantly, more flat) performance than lock-based barriers supported by existing microprocessors.