Error detecting multiple block (d,k) codes
L. Fredrickson, Jack K. Wolf · IEEE Transactions on Magnetics · 1989
The authors present a construction for two families of error detecting multiple block (d,k) codes. The first family has the ability to detect when encoded blocks have become offset in time by a single bit cell, while the second family has the ability to detect when a one in an encoded block is misdetected and appears in an adjacent bit cell. The authors present sub-block constructions for the two families of error detecting (d,k) codes and maximize the code rate over the set of all legitimate (d,k) codes formed from single and multiple sub-blocks. It is noted that, for both families of error detection codes, the construction is able to retain over half of the (d,k) sequences of a given length usable in a non-error-detecting block code. Therefore, using this construction, a non-error-detecting (d,k) block code which encodes m binary bits to an average of n channel bits can be converted to an error detecting (d,k) block with a rate loss of at most 1/n.>