An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet Transform
Leibo Liu Hongying Meng, Milin Zhang · 2006
An ASIC implementation of Spatial Combinative Lifting Algorithm (SCLA) based 2-D forward and inverse Discrete Wavelet Transform (DWT) with both 5/3 and 9/7 filters and 5-level Mallat decomposition is proposed in this paper. This processor is fabricated in a 1.5mm × 1.5 mm die, using UMC 0.18um CMOS technology, containing 28K gates plus 47Kbits on-chip SRAM. Test shows this chip can process at 23.29frames/s with image resolution up to 1920×1080 pixels (YUV422 full color) under 100MHz, and consuming 50mW under a 1.8V power supply.