Real-Time Digital Video Stabilization on an FPGA
Luis Araneda, Miguel E. Figueroa · 2014
We present a hardware architecture for real-time digital video stabilization in high-performance embedded systems. The stabilization algorithm analyzes the current and past video frames and obtains a motion estimation vector, which is then filtered to isolate unwanted camera movements from intentional panning. The vector is then used to correct the output video frame. We designed a hardware architecture for motion estimation, filtering and correction and implemented it on a Xilinx Spartan-6 LX45 Field Programmable Gate Array (FPGA). Running on the 640x480-pixel video output of an infrared camera, the circuit successfully compensates involuntary camera motion at a maximum throughput of 104.15 frames per second and dissipates 24.16mW of power with a 100MHz clock.