The automatic generation of bus-interface models
Y.-H. Leong, William P. Birmingham · Design Automation Conference · 1992
The authors describe a system, HIDE, that automatically creates very high-speed IC description language (VHDL) bus-interface models from timing and bus-state diagrams. The information required by HIDE is easily found in component documentation. Thus, HIDE reduces the time for understanding a component's operation and for writing the model. An Intel iAPX80386 model was developed in less than one week. HIDE can also be used to develop executable specifications, as its inputs are a normal element of the IC design process. >