Design of compact reversible decimal adder using RPS gates
Rekha K. James, K. Poulose Jacob, Sreela Sasi · 2012
This paper presents two universal 4×4 ‘reversible RPS gates’ that can function as a reversible 4-bit Binary to BCD converter with a garbage count of zero. The new ‘fully or partially reversible RPS gate’ gives an optimized design of the offset correction circuit of a reversible Binary Coded Decimal (BCD) adder. The paper proposes reversible implementations of BCD adder using fully reversible RPS gates and using combination of HNC-RPS (fully and partially) gates; and the comparisons are tabulated. The HNG-RPS designs achieve a reduction in garbage outputs and logical complexity compared to the existing reversible BCD adder designs. This can form the basic building block of a high speed decimal ‘Arithmetic and Logic Unit (ALU)’ for a low power reversible ‘Central Processing Unit (CPU)’.