A high performance factoring machine
W. G. Rudd, Duncan A. Buell, Donald M. Chiarulli · ACM SIGARCH Computer Architecture News · 1984
Factoring, primality testing, and other problems of current interest [1, 2, 3, 4, 5, for example] in experimental number theory require machines with different architectures from those for any other application. Algorithms for such problems are small, but their execution requires high-speed arithmetic on very long integers interspersed with shorter precision computing that can conveniently be done by several processors acting in parallel. In this paper, we describe the preliminary design of a processor specifically for computational number theoretic problems. The primary component is a 256-bit ALU which is dynamically reconfigurable to provide for parallel independent operations on groups of 32-bit subwords within the 256-bit word.