Area-efficient FPGA-based FFT processor
Trini Sansaloni, A. Pérez-Pascual, Javier Valls · Electronics Letters · 2003
A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the ‘twiddle factors’ sequentially leads to an area saving up to 35% with respect to other cores.