Hybrid compilation
Raghavendra Rao Loka · ACM SIGPLAN Notices · 2005
Compilers normally use the same technique to translate all routine level units regardless of the complexity, or the cost/benefit ratio of the effort. This would lead to unnecessary increase in compile time if there are too many simple routines. This note describes a hybrid scheme used in a hardware design compiler to overcome this problem. The compile times have been reduced by 10% across all the inputs-in the domain of hardware design compilation with this technique. The note also describes what the original goal was, and the compromises made to deal with reality.