Communication synchronous scheme for MPSoC
Chunhua Chen, Gaoming Du, Duoli Zhang, Yukun Song, Ning Hou · 2010
Inter-Processor communication synchronization in multi-processor system-on-chip (MPSoC) is one of the key factors for the whole chip performance. It cannot only affect the efficiency of task-level parallelism, but also has high dependency on MPSoC hardware architecture. Two synchronization mechanisms, i.e. mailbox and packet switching, are studied and analyzed in Network on chip based MPSoC. At first, the two schemes are implemented and verified in stand-alone mode, analyzed with communication latency, communication bandwidth and resource utilization. Furthermore, the two schemes are analyzed in MPSoC prototype environment that runs real-time fade-in fade-out video processing. Experimental results show that the mailbox based synchronization scheme has low latency and low resource overhead, but it is not feasible for large number of clusters due to the physical limitation. Although the packet based scheme has more latency, it has more scalability and feasibility.