RNS based reconfigurable processor for high speed signal processing
Partha Garai, Chaitali Biswas Dutta · 2014
Digital signal processing requires a large number of mathematical operations to be performed in high speed real time mode and repeatedly on a set of input data. The power requirements of the DSPs are increasing day by day along with the processing speed and chip area. Because of the limitation of power supply and space, mobile devices cannot use the general purpose processors to process digital signals, but a specialized DSP is required to provide a high performance - low cost solution. So, rather than traditional number systems, Residue Number System (RNS) is becoming attractive for their capabilities for performing addition and multiplication operation efficiently. A guideline for a novel Reconfigurable DSP Processor is proposed in this paper, based on the formulation of the Chinese remainder theorem and RNS, that can process any function using dynamic reconfigurability, which are the collections of some basic operations. Because of the Carry-free nature of RNS, this scheme can be implemented in Mobile and Wireless Computing and other fields where high speed computations are required with limited resources. The proposed architecture has been validated on Field Programmable Gate Array (FPGA).