Hardware acceleration and verification of systems designed with hardware description languages (HDL)
Remigiusz Wiśniewski, Marek Węgrzyn · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2005
Hardware description languages (HDLs) allow creating bigger and bigger designs nowadays. The size of prototyped systems very often exceeds million gates. Therefore verification process of the designs takes several hours or even days. The solution for this problem can be solved by hardware acceleration of simulation.