Design and Comparision of Rs Encoder and Rs Decoder on Family of Cyclone FPGA Using VHDL
Hitesh G Kamani · International Journal of Scientific Research · 2012
In this paper design of Reed Solomon (255,239) Encoder and Decoder and perform this Codec on family of Cyclone FPGA and compare the performance based on area occupied by the design and the speed at which the design can run and power dissipation. I applied forward error correction system to improve the overall performance of the system. The implementation is Written in VHDL based on Barlekamp Massy, Forney and Chien Search Algorithm. Design and Comparision of Rs Encoder and Rs Decoder on Family of Cyclone FPGA Using VHDL