New Self‐dual Circuits for Error Detection and Testing
А. Л. Дмитриев, V. Saposhnikov, V.V. Saposhnikov, Michael Göessel, Vl. Moshanin, A. Morosov · VLSI design · 1999
In this paper new methods for the transformation of a given combinational circuit into a self‐dual circuit based on the notion of a self‐dual complement are investigated. The large variety of self‐dual complements can be utilized to optimize the transformed self‐dual circuit. Self‐dual duplication and self‐dual parity prediction are considered in detail. As a method for the reduction of self‐dual outputs, output space compaction of self‐dual outputs is considered. For the first time we also describe in this paper how a self‐dual circuit can be modified into a self‐dual fault‐secure circuit.