A distributive D-algorithm for generating the test pattern for faulty combinational circuit
Hao‐Yung Lo, Chien-Chun Su · International Journal of Electronics · 1989
In this paper we propose a method for generating test patterns very efficient for stuck-at faults, either in symmetric or unsymmetric circuits. The faulty symbol D or D is distributed like any binary variable, from the site of source to the primary output passing through all possible paths. The test pattern for the stuck-at fault is generated by only one backtrack and simultaneously determined whether the test pattern exists or not. There is therefore no need for tracing paths forwards and backwards several times as the conventional D-algorithm or the modified version of D-algorithm during the process of the test pattern generation.