Bit-level partial evaluation of synchronous circuits
Sarah E. Thompson, Alan Mycroft · 2006
Partial evaluation has been known for some time to be very effective when applied to software; in this paper we demonstrate that it can also be usefully applied to hardware. We present a bit-level algorithm that supports the offline partial evaluation of synchronous digital circuits. Full PE of combinational logic is noted to be equivalent to Boolean minimisation. A loop unrolling technique, supporting both partial and full unrolling, is described. Experimental results are given, showing that partial evaluation of a simple micro-processor against a ROM image is equivalent to compiling the ROM program directly into low level hardware.