Timing analysis challenges for high speed CPUs at 90nm and below
Avi Efrati, Moshe Kleyner · 2002
Advances of the VLSI technology into the sub-90nm processes, enabling complex CPU designs that work at GHz frequencies pose numerous design and verification challenges.In this invited presentation, we focus on challenges in timing analysis of CPUs working at GHz speeds and sub-90nm processes.We start by brief overview of Timing Analysis tool used for intel CPUs and the "shell" timing models used for large blocks and how they integrate into full-chip model. Hierarchical timing is emphasized as key enabler for handling full-chip timing.Next, short-term challenges are presented: