The phoney war [hardware-description languages]
C. Edwards · Electronic Systems and Software · 2004
The arrival of Systemverilog on the hardware-description language scene has caused a lot of confusion. But experts are finding separate roles for SystemC and Systemverilog. Nothing attracts controversy in electronic design automation (EDA) the way the choice over design language does. It's entirely understandable. Experience in a particular language can pigeonhole a designer very quickly, especially if it looks like your chosen language seems to be turning into the Cobol of chip design; it's tough getting a job if you only know Ella. The question facing many designers now is whether to learn SystemC or Systemverilog, maybe both.