Thermal Aware Processor Operation Point Management
Naga Pavan Kumar Gorti, Arun K. Somani · 2012
Existing schemes for dynamic voltage and frequency scaling (DVFS) do not account for the intertask thermal cycles. The chip reliability testing process usually also is not inclusive of test cases quantifying the chip reliability in the presence of small scale thermal cycles. However, a good number of in-field chip failures are attributed to the consequences of thermal cycles. Thus, it is imperative to include their effects into the processor voltage and frequency selection process. Our work focuses on developing an integrated processor thermal and performance management system centered on novel polynomial time scheduling algorithms that achieve minimal thermal cycle guarantees in soft real time environments. Our scheme leverages application awareness and runtime monitoring for improving the lifetime of the chip, while achieving considerable energy savings. Our scheme shows a significant reduction in thermal cycles and peaks, leading to longer chip life expectations. Our results indicate a 10 fold increase in the expected chip lifetime and 50% energy savings compared to operation at the rated maximum voltage and frequency.