A datapath classification method for FPGA-based scientific application accelerator systems
Yui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko F. Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri · 2010
Resource reduction design techniques play an important role to implement large-scale FPGA-based accelerator systems in floating point applications since available resources on FPGAs are limited. This paper proposes a dataflow graph classification method which makes groups of graphs based on their similarity in order to bring out efficient graph combining. Aiming at finding effective parameters for the k-means algorithm, various parameter combinations are evaluated and compared in terms of resource reduction effects and performance. The experimental results using an FPGA-based biochemical simulator reveal that the graph clustering that uses information on the maximum common subgraphs achieve 73.3% of resource reduction rate while alleviating the performance degradation.