A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface
Dean Nobunaga, E. Abedifard, Frankie Roohparvar, June Lee, Erwin Yu, Allahyar Vahidimowlavi, Michael Abraham, S. Talreja, Rajesh Sundaram, Rod Rozman, Luyen Vu, Chih Liang Chen, Uday Chandrasekhar, R. Bains, Vimon Viajedor, William Mak, Munseork Choi, Darshak Udeshi, Michelle Luo, Shahid Qureshi · 2008
A 3.3V 8Gb NAND flash memory with a synchronous double-data-rate (DDR) interface is designed and fabricated using 3M 50nm technology to meet the requirements of the markets. This paper achieves a NAND flash program throughput of 100 MB/s with quad-plane operation, which is 5x previously reported. I/O read/write throughput of 200MB/s is achieved using a newly developed DDR interface and data path. The chip features a dual interface, supporting both the newly developed synchronous DDR interface as well as the standard, asynchronous NAND flash interface.