Architecture-level analysis and evaluation of transient errors on NoC
Jiajia Jiao, Yuzhuo Fu, Jiang Jiang · 2011
Scaling IC technology, lower voltage supply and high frequency etc cause transient errors to dominate in VLSI reliability design. NoC, as the most promising communication infrastructure for many-core system, also faces bits upset challenge due to transient errors. In this paper, we focus on analysis and evaluation of transient errors on NoC from architecture perspective: 1) classify the transient errors in NoC and analyse the cross-relationship between different types of errors to explore fine grain transient errors effect; 2) define the unified architecture-level metrics for evaluating transient errors effect on performance and reliability to guide fault tolerance methods selection; 3) do some cases study about transient errors in NoC based on accurate simulation results to validate our approach.