A single chip multi-functional DDS waveform generator based on FPGA with SOPC design flow
Yue Ruan, Ying Tang, Wenji Yao, Zhangquan Wang, Sen Xu · 2012
This work presents a highly integrated single chip multi-functional, multi-waveform signal generator which can generate various waveforms, with digital controller inside to adapt embedded and low power applications. The proposed system is composed by Nios II, DDS (Direct Digital Synthesis) and other peripherals. Nios II is a reconfigurable, programmable and optimizable soft-core embedded CPU. DDS is used to generate required waveforms. Together with modern EDA tools, the system HW/SW co-design and FPGA implementation is accomplished, using typical SOPC design flow. Utilizing characteristics of Nios II, the core and peripheral logical units that system need are put together and implanted into a single FPGA chip. The Avalon bus is used to connect peripheral modules (such as function switch buttons and 7-segment LED display units) to Nios II's Avalon bus main port (instruction and data control port). The realized system is flexible to reduce, extend, with low power consumption, and has System on Programmable Chip (SOPC) function which means the system's software and hardware is online programmable.