Single-ended SRAM with high test coverage and short test time
Chua‐Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia‐Hsiung Kao · IEEE Journal of Solid-State Circuits · 2000
The advantages of low power dissipation and smaller chip area for single-ended SRAMs are well known. In this paper, we present the configuration and test strategy of a single-ended, six-transistor SRAM. The benefits of short test time, no retention test, and high test coverage are verified. The goals of low power, high quality control, and short test time of the full CMOS SRAM can be achieved.