A Wrapper for Low-Power Error-Correcting Data Delivery in On-Chip Networks
Chia‐Ming Wu, Hsin-Chou Chi, Ying-ming Huang · 2006
Network-on-chip (NoC) design provides designers a communication infrastructure to integrate heterogeneous intellectual property (IP) cores. To reuse IPs based on shared buses in the NoC architecture, an interface is needed for the NoC communication protocol. In this paper, we present a wrapper design for low-power error-correcting data delivery in on-chip networks. Our wrapper not only provides an interface for reusing IP cores based on the AMBA bus, but also lowers down power dissipation and improves robustness of data transmission. We have implemented this IP wrapper using cell-based design with UMC 0.18 mum technology. It shows that the wrapper design is feasible and efficient.