Power Optimization Techniques for DDR3 SDRAM
Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma · 2015
With memory contributing to a significant fraction of the overall power consumption, several power management techniques targeting the memory sub-system have been proposed by researchers. In this work, we propose two memory power optimization techniques. We first suggest dynamically varying the queue structure in a memory controller, and next propose an adaptive threshold technique for switching to low power SELF-REFRESH operating mode of the DDR3 SDRAM. With the proposed queue-resizing optimization, the power consumption reduces by up to 93%, while the adaptive threshold technique results in an additional 21% power savings, on an average, over a constant threshold implementation.