Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space
Chia-Yu Yao, Wei‐Chun Hsia, Yung-Hsiang Ho · IEEE Transactions on Circuits and Systems I Regular Papers · 2013
This paper presents a practical method for designing fixed-point FIR filters. The proposed method takes both the filter's magnitude response and its hardware cost into consideration in the design process. The method constructs a basis set based on the fixed-point coefficients that have been synthesized already. The elements in the basis set are used to synthesize the undetermined fixed-point coefficients later. Thus, this basis set expands gradually along with the progress of the coefficient design. The method employs some strategies to speed up the design process. For example, a complexity estimation strategy helps us stop digging deeper in some branches of the search tree, and a solution prediction strategy for high-order FIR filters helps us design fixed-point FIR filters of length equal to a few hundreds. Applying the proposed method to design twenty benchmark cases, we can obtain hardware-efficient results in a reasonable design time. In two long filter design cases, our design results are better than those designed by the other methods.