Performance analysis of advanced encryption standard for low power and area applications
Trapti Sharma, R. Thilagavathy · 2013
This paper presents a very low power and area efficient ASIC implementation of Advanced Encryption Standard Algorithm (AES). The implementation results of S-Box, MixColumn Transformation and overall AES encryption/ decryption are given in this paper. The AES has been implemented in 90nm standard CMOS library using Synopsys Design Compiler with a core voltage of 1.2V. The power dissipation of S-Box implementation is 16.2 μW at 10 MHz clock frequency. The Total power dissipation and area of AES-128 bit implementation is 224 μW and 50377 μm2respectively at 10 MHz with a delay of 13ns which is lower than the existing architectures. The maximum operating frequency of the proposed design is 200MHz. For the purpose of comparison the proposed design was also implemented in 180nm CMOS technology.