Extended Word-Line NAND Flash Memory
Jang-Gn Yun, Il Han Park, Wandong Kim, Jong Duk Lee, Byung‐Gook Park · Japanese Journal of Applied Physics · 2009
A NAND flash memory array having extended word-lines is proposed. Without scarifying areal density, both physical gate length and charge storage node size are increased through the word-line extension process. Simple fabrication flow is delivered and device performances in a viewpoint of the short channel effect are simulated. The effect of gate length variation on the cell threshold voltage ( V TH ) distribution is addressed. Programming characteristics in the inversion-type source/drain NAND flash memory are also described. Some side effects concerned with the program disturbance and cell-to-cell interference are investigated in comparison with the conventional NAND flash memory.