VLSI architecture for discrete wavelet transform
Grzeszczak, Yeap, Panchanathan · 1994
This paper presents a new VLSI architecture for computing the discrete wavelet transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI.>