Intel Xeon Phi: Various HPC aspects
Kapil Mathur, Sandeep R. Agrawal, Shraddha Desai, Deepti Malav, C. V. Deepu, Goldi Misra · 2013
Many times enablement of highly parallel applications to deliver very high performance is quite a tough task. This can be because of bottlenecks in the underlying hardware subsystems or overheads imposed by the parallel programming models used. Software development tools play an important role to understand and minimize these bottlenecks. Hence success of an emerging architecture is related to availability of such tools, and support for existing parallel programming models and techniques. Also, computational performance per watt is an important consideration in making the choice of the hardware subsystem. In this poster we have attempted to bring out such HPC aspects of Intel Xeon Phi, a many-core architecture recently launched by Intel.