Accommodating memory latency in a low-cost rasterizer
Bruce Anderson, Andy Stewart, Robert J.B. Macaulay, Turner Whitted · 1997
This paper describes design tradeoffs in a very low cost raster&r circuit targeted for use in a video game console.The greatest single factor affecting such a design is the character of memory to which the image generator is connected.Low costs generally constrain the memory dedicated to image generation to be a single package with a single set of address and data lines.While overnll memory bandwidth determines the upper limit of performance in such a small image generator, memory latency has n fnr greater effect on the design.The use of Rambus memory provides more than enough aggregate bnndwidth for a frame buffer as long as blocks of pixels nre moved in each transfer, but its high latency can stall nny processor not matched to the memory.The design described here utilizes a long pixel pipeline to match its internal processing latency to the external fmme buffer memory latency.