A hardware simulation engine based on decision diagrams (short paper)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno · 2000
A hardware logic simulation engine based on decision diagrams is presented.For the data structure of the engine, we propose PMDDs (Paged reduced ordered Multi-valued Decision Diagrams).A unit of this engine consists of memory (RAMs) and con trol circuits: RAMs store the PMDD data, and the control circuits trace the edges according to the input vectors.The engine consists of several units, and is accelerated by pipelining.Experimental results using a prototype are shown.