Generation of Multi-Cycle Broadside Tests
Irith Pomeranz · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2011
The use of multi-cycle (or multi-pattern) tests for delay faults can reduce the number of clock cycles required for test application, and enhance the ability of a test set to detect delay defects. This is achieved by exercising the circuit in functional mode for several clock cycles as part of each test. This advantage is especially important for multi-pattern functional broadside tests, which guarantee normal functional operation conditions during the functional clock cycles of the test. This paper describes a procedure for generating multi-pattern broadside tests. The procedure extends a two-pattern test set gradually to increase the number of patterns included in each test while reducing the number of tests. Experimental results demonstrate that significant reductions in the numbers of clock cycles are possible with the proposed procedure for both functional and arbitrary broadside test sets.