A knowledge-based test generator for standard cell and iterative array logic circuits
P. Varma, Yoshihiro Tohma · IEEE Journal of Solid-State Circuits · 1988
The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays is described. Protean comprises a cell test generator, which generates test knowledge and propagation characteristics for cells, and a hierarchical test generator, which uses this high-level test knowledge in conjunction with low-level structural information to generate tests for the circuit.>