A flow regulator for On-Chip Communication
Zhonghai Lu, Dimitris Brachos, Axel Jantsch · 2009
We have proposed (¿, ¿)-based flow regulation as a design instrument for system-on-chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where ¿ bounds the traffic burstiness and ¿ the traffic rate. In this paper, we present a hardware implementation of the regulator. We discuss its microarchitecture. Based on this microarchitecture, we design, implement and synthesize a multi-flow regulator for AXI. Our experiments show the effectiveness of such a regulation device on the control of delay, jitter and buffer requirements.