Implementations of Low-Cost Hardware Sharing Architectures for Fast 8 x 8 and 4 x 4 Integer Transforms in H.264/AVC
Chih‐Peng Fan, Yen‐Nan Lin · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2007
In this paper, novel hardware sharing architectures are proposed for realizations of fast 4 × 4 and 8 × 8 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 4 × 4 and 8 × 8 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 4 × 4 and individual 8 × 8 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125 MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.