Discrete wavelet transform implementation based on FPGA
Juan Li, Binghua Su, Yongming Yan, Caigao Jiang · 2012
In this paper, a semi-cache parallel circuit structure which is based on FPGA process system combined with the existing Mallat discrete wavelet transform algorithm is introduced. The virtex-6 FPGA development board implements this structure in real-time, and the functional modules of DSP48E1 in the virtex-6 serves as the improvement of data accuracy. Modelsim is responsible for simulation of each module unit in Verilog HDL. Compared with the conventional algorithm, this architecture reduces half of the on-chip storage resources. Besides, in comparison with the performance of processing time on OMAP3530, Simulation results demonstrate that this state-of-art method shows more superiority.