A single chip architecture for multiprocessor DSP
Chris Brown · 1995
This paper describes a single chip multiprocessor for sparse matrix multiplications that efficiently exploits parallelism. The device uses cache RAM to minimise the memory bandwidth required. Access to the cache RAM is restricted to the external system so that the processors cannot cause inconsistencies in the data held in the caches. The processors are connected to the cache RAMs directly. Many multiprocessors use a cross bar switch to connect the processors and the cache RAM, but this has been shown to be inefficient and unnecessary. Mapping algorithms onto the system has been demonstrated using the wavelet transform. (6 pages)