FMEA-based analysis of a Network-on-Chip for mixed-critical systems
Eberle A. Rambo, Alexander Tschiene, Jonas Diemer, Leonie Ahrendts, Rolf Ernst · 2014
Network-on-Chip-based multi- and many-core architectures show high potential for use in safety-critical real-time applications, such as Flight Management Systems, considering their superior efficiency. For such use however, safety standards require proof that the architecture meets the specified security goals. This usually involves a Failure Mode and Effects Analysis (FMEA) to reveal the effects of all potential failures. Moreover, the Network-on-Chip (NoC) is a shared component and plays central role in a mixed-critical system, which must guarantee the isolation between tasks, that may have distinct criticality levels. We present an FMEA-based system-level analysis for NoCs designed for mixed-critical systems. It comprises FMEA, error effects classification regarding duration and isolation violation, and technology independent probability assessment. The analysis gives effective insight into fault-related weaknesses of the NoC, and enables considerable improvements to the NoC's resilience with minimal overhead. We apply it to a typical packet-switched NoC and present the results. Although developed for safety critical applications, the approach can be applied to improve the robustness of general systems.