Accelerating intellectual property design flow using Simulink/sup /spl reg// for system on a programmable chip
Philippe Molson · 2001
This paper discusses how the IP MathWorks/sup /spl reg// Simulink/sup /spl reg// tools speed up the integration of intellectual property in a system on a programmable chip. The DSP Builder tool enables this flow by providing an automated translation of a bit and cycle accurate C++ Simulink/sup /spl reg// model into a VHDL hardware implementation. The coding style guidelines to write system level re-useable IP models highlight how to take advantage of the polymorphism and object oriented nature of C++ in this particular context.