Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints
S. Yalamanchili, L. Te Winkel, D. Perschbacher, Belle Shenoy · Concurrency Practice and Experience · 1995
Abstract The paper focuses on the problem of partitioning and mapping parallel programs onto heterogeneous embedded multiprocessor architectures for real‐time applications. Such applications present unique constraints and challenges. In addition to heterogeneity, the proposed partitioning and mapping algorithms satisfy memory, task throughput, task placement, intertask communication bandwidth, and co‐location constraints. They do so for architectures that utilize circuit‐switched (rather than packet‐switched) interprocessor communication and optimize latency and throughput in addition to load‐balancing. Finally, these mapping algorithms make use of knowledge of the local scheduling discipline to accommodate real‐time scheduling constraints. Our focus is on unstructured parallel programs that fall into one of two classes: (i) the class of computations characteristic of control applications in a real‐time environment where tasks execute concurrently, periodically exchanging information, and (ii) pipelined computation graphs found in sensor data processing applications. The algorithms are implemented in a set of tools that operate with commercial CASE tools at one end, and present an interface to multiprocessor simulators at the other end. Collectively, the algorithms form a significant component of an interactive design environment for the development and mapping of real‐time embedded parallel programs. The paper describes the algorithms, the encapsulating toolset, and presents an example of their application to an existing embedded application—an Autonomous Underwater Vehicle application.