A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
Gary S. Ditlow, Robert K. Montoye, S.N. Storino, S.M. Dance, Sebastian Ehrenreich, Bruce Fleischer, Thomas Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter Wendel, Leland Chang · 2011
In multi-ported register files, memory cell size grows quadratically with the total number of ports due to wordline and bitline wiring. Reducing the number of physical access ports in a memory cell can thus lead to significant area and power savings as well as latency improvement. Double-pumped register files operate access ports twice in a single clock period to reduce area by halving the number of physical ports in the memory cell-a technique often confined to low-frequency applications. Replication of a memory cell in separate arrays halves the number of physical read ports in each copy. In this work, double-pumped write ports and replicated read ports are applied to a 4R2W register file in a high performance microprocessor product. This paper describes detailed implementation and measured hardware characteristics of this array and demonstrates a fast error correction scheme. The techniques used balance high efficiency and low latency and thus differ from previous work, in which double pumped ports perform a write followed by a read in a very large register file or where write ports are double-pumped without cell-level read port reduction.