Design rule check on the clock gating logic for testability and beyond
Kun-Han Hans Tsai, Shuo Sheng · 2013
The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed to handle the design with such rule violations to prevent simulation mismatches while minimizing the test coverage lost.