A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes
Jeff S. Reeve, K. Amarasinghe · 2004
We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has a restricted complexity in the number of communications to or from and the processor cannot exceed 4 for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and demonstrate the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes.