Model reduction techniques for the formal verification of hardware dependent software
Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten · 2010
Contemporary researches provide many solutions for formally verifying both hardware and software systems. In this paper, we describe the formal verification of assembly programs, which are part of the HW/SW interface in hybrid systems. We have developed several methods to model assembly programs in VHDL in order to verify their functionality. Our discussion will show that, by applying different reduction methods, we managed to formally verify the correctness of iterative algorithms with execution times higher than 6000 clock cycles.