Reconfiguration of high performance VLSI sub-arrays
Jun Wu, Thambipillai Srikanthan · IEE Proceedings - Circuits Devices and Systems · 2006
Reconfigurable techniques attempt to realise maximum possible fault-free sub-arrays in mesh connected VLSI arrays with faulty elements. Although this problem has been investigated extensively, the performance of the resulting sub-arrays has not been addressed fully. In this paper, techniques for finding the high performance target array (HPTA) in the given VLSI array are proposed. First, it is shown that finding an HPTA in the given VLSI array is equivalent to solving a typical optimisation problem of multistage decision. Then a heuristic algorithm is presented based on dynamic programming for an HPTA. The proposed algorithm minimises the interconnect length of the target array by revising each original logical column to the optimal one without sacrificing on the size of the sub-array. Simulation results conclusively show that the proposed algorithm reduces the number of long interconnects in the sub-array without loss of harvest.