Virtual address cache with no reverse address buffering
Lanfranco Lopriore · Proceedings of the IEEE · 1988
A virtual address cache memory, whose operation is controlled explicitly by software, is presented. Ad hoc hardware mechanisms, including machine instructions and an operand addressing mode, reduce the complexity of cache management logic in favor of the capacity of the cache, and solve the major problem of virtual address cache organization: two or more virtual addresses mapping into the same real address.>